ADP Dual Boostrapped 12 V MOSFET Driver with Output Disable The ADP is a dual, high voltage MOSFET driver optimized for driving two N- channel. Compatibility. Pinout identical, but electrical specifications, package and temperature range may vary. Rochester Electronics and Arrow Supply Assurance have. The ADP is a dual high-voltage MOSFET driver optimized for driving two N- channel MOSFETs which are the two switches in a non-isolated synchronous.
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Driver with Output Disable. All-in-one synchronous buck driver. One of the drivers datashet be bootstrapped, and is designed to. The ADP includes overlapping drive. Multiphase desktop CPU supplies.
The OD pin shuts off both the high-side and the. Single-supply synchronous buck converters. The ADP is specified over the commercial temperature. C, and is available in an 8-lead SOIC. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its daasheet, nor for any.
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One Technology Way, P. BoxNorwood, MAU. Specifications subject to change without notice. No license is granted by implication. Pin Configuration and Function Descriptions PC Board Layout Considerations Updated Figure 1; Deleted Figure Updated Theory of Operation Change to Ordering Guide Change to General Description Change to Figure B Page 2 of C, unless otherwise noted.
ADP3418: Dual Bootstrapped, 12 V MOSFET Driver with Output Disable
Output Resistance, Sourcing Current. Output Resistance, Sinking Current. For propagation delays, t pdh refers to the specified signal going high, and t pdl refers to it going low. B Page 3 of Stresses above those listed under Absolute Maximum Ratings.
This is a stress. Absolute maximum ratings apply individually. Unless otherwise specified, all voltages. All Other Inputs and Outputs. Lead Temperature Soldering, 10 s. ESD electrostatic discharge sensitive device. Electrostatic charges as high as V readily accumulate on. Although this product features.
Therefore, proper ESD precautions are recommended to avoid performance.
B Page 4 of The capacitor should be between nF and 1? This pin has primary control datashet the drive outputs. It is the floating return for. B Page 5 of Output Disable Timing Diagram. B Page 6 of B Page 7 of B Page 8 of The overlap protection circuit prevents both of the main power.
A single PWM input signal is all that is required to. The overlap protection circuit. A more detailed description of the ADP and its features. Refer to Figure 1. Q1 turn off to the Q2 aadp3418 on, and by internally setting the. Xdp3418 low-side driver is designed to drive a ground-referenced. To prevent the overlap of the gate drives during the Q1 turn off.
The bias to the low-side driver is internally. When the PWM input signal goes low, Q1 will. Before Q2 can turn. When the driver is enabled, the driver’s output is degrees. When the ADP is dis. Once the voltage on the SW pin has fallen to. If the SW pin had not gone high first. The high-side driver is designed to drive a floating N-channel.
The bias voltage for the high-side driver is developed. Q2 turns on, regardless of variations in temperature, supply. The bootstrap circuit comprises a diode, D1, and bootstrap. To prevent the overlap xatasheet the gate drives during the Q2 turn off. Information section for more details. When the ADP is. When the PWM input signal goes high. When the PWM input goes.
Q2 will begin to turn off after a propagation delaybut before. Q1 can turn on, the overlap protection circuit waits for the. Once the voltage at DRVL has reached this point, the overlap. To complete the cycle, Q1 is switched off by pulling the gate. Once the delay period has expired, Q1 will begin turn on. Q2, turns on, the SW pin is pulled to ground. The high-side driver’s output is in phase with the PWM input. When the driver is disabled, the high-side gate is held low.
B Page 9 of A small-signal diode can be used for the bootstrap diode due to.
The average forward current can be. Multilayer ceramic chip MLCC capacitors provide.
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The peak surge current rating should be calculated. The bootstrap circuit uses a charge storage capacitor C BST and. These components can be. A minimum 50 V. The capacitor values are determined. It is also highly recommended to use the Boot-Snap circuit to. If a simple bootstrap arrangement is used, make.
C Xatasheet can then be found by rearranging Equation 1: Yet, there is also a significant source lead inductance that.
For example, an NTD60N02 has a total gate charge of about. R Datawheet is used for slew-rate limiting to minimize the ringing at the. It also provides peak current limiting through D1.
An R BST value of 1. This will create a. B Page 10 of Once you have this specification, the next step is to.